Figures I got to explain this...
Sounds confusing - yes it is, but in the circuit - the Pin 7 - SINKS current - meaning when I say high - lets power flow into it...letting the transistors' base it has connected to it - turn on.
In this instance Q31 and Q33 both are turned on, but remember NPN inverts - while PNP needs inverted with respect to NPN to operate - inverted.
So with Q31 and Q33 on, and PLL Pin 6 in LOCK - Q32 turns off and this works, which is why I made up the "see-saw" graphic to help understand the forcing RX level versus the Sensitivity TX side would have - in changes to PLL Pin 6 condition.
This is due to the nature of single ended power supplies - the Op-Amp inputs needs a working pull down and pull up network to "lift" the signal detection and it's threshold is fixed, using biasing schemes like this.
So Pin 6 PLL "check" for Go-no go condition - is weighted differently than the MIC Pin 3 detect used on Pin 5. Since Pin 5 is the inverted input - this also looks at Pin 7 condition - with Pin 6 in the balance...
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