Handy andy Igoing to do this
Lets look further back, into the PLL itself - ok look at pins 1 and 2 as a set, and Pins 3 and 4 as a SEPARATE set. Also Pin 5 and where it is in a loop caught up in those pins. There is also a Pin 6 with a Diode designed to FORCE or Pull power from a line. Follow that line it's goes to a lot of places including the MB3756 Regulator...But come back because we have to see why this, nearly entire half of the chip, isn't oscillating too. Because R163 is a 22K - its'; for the use of Pull-up to keep marginal locks working unless there is a catastrophic failure of the system. Marginal locks? Yes, thermal is one, voltage dropouts from Rx/Tx switching issues - are another, otherwise a slow cap that takes too long to charge onto something pulling down Regulated voltages the PLL looks to - and causing it's own on-board regulator to shift drivers - yes a PLL needs an on-board regulator too so you know...
Notice where and how TP9 works and where it is, it's using the PLL free-running loop pins 1-2 and 3-4
These two pairs form a free running "gated" oscillator - one high speed, another low speed. Between the two - is where Pin 17 is "compared" and if it misses - it sets a count - and too many misses generate a output on Pin 5 - Pin 5 is your correction to the Varactors' ability to make L21, L19 and L21 work...
You mentioned L17 - I think you meant L21 or even L20 - L17 is where? on your board? (it's a coil so it would show a short) Maybe you can scope that one side at a time - and you'd have MHz (Read a LOT OF HERTZ) of frequency on one side but not so many MHz on the other (attenuated) - it's a low-frequency choke - like power supplies use...take a higher frequency ripple and smooth's it out - its is not perfect nor is it used in that fashion - just acts as a high impedance doorway - to keep high-frequency out (stays with the VCO side) and let low-frequency (the Clock Errors - your BEAT Frequency differences) pass into Pin 17 to cycle with the other half f the chip.
Now, if you are getting 33 MHz then it looks like you now have the UHIC chip running, you're just not getting the PLL gating event to compare to Pin 17 - so scope the 1-2 pin and 3-4 pin with a high-impedance probe looking for about 10MHz for starters to see if you can see "clocking" going on.
Why the 1-2 and 3-4 pins? Well, Pin 5 is needed so that the PLL thinks it's ok to compare Pin 17's frequency input and send any data out - thru Pin 5 - so it looks and uses 1-2 and 3-4 mess that cycles - to generate either a pulse or hold low - to correct the Varactor. So if 1-2 and 3-4 are not "oscillating" - Pin 5 won't work and so the PLL thinks something's wrong and sets Pin 6 to lock out everybody from using the signal present.
- What can throw you for a loop here (SIC) is the fact that the TP9 has both DC and a weak AC component to it on the same line at the same time. If C90 (R104 / C90) is bad or shorted, you'll have too low of power to even get the oscillator to start. so look for and check values on that TP9 line...
That is part of the loop Pin 17 uses to compare to the mess going on in the VCO (Your UHIC chip) - TR20 "beats" with it...So verify you even have a clock of ~10MHz (from your Xtal) see straight above the Cobra 148FGTL one, there is a TP13 - check QUALITY of signal - degradation means you have parts not in tolerance - so it is not "Clean enough" to be used to check for any sort of clock event
- the PLL may shut down - simply because even the Crystal may be too weak to send a good quality resonate signal - it's more noise than a single vibrational frequency.. Your Xtal goes in, and then on another pin it goes out. Notice there may be a cap or two of small Pico-farad ratings between lines (like C85 - 22pF) - this is what helps in keeping the signal "clean" - a feedback path to help the PLL generate proper clocking levels.
#37Handy Andy,
Yesterday at 3:28 PM
Last edited: Today at 1:21 PM